Many factors are included in a microprocessor design process to ensure that the microprocessor will operate as expected across anticipated, and even many unanticipated, workload conditions. Many processes use both higher-level models of the microprocessor design (e.g., coarse-grained models, such as so-called “performance models”) and lower-level models of the microprocessor design (e.g., fine-grained models, such as so-called “register transfer logic (RTL) models”) to evaluate designs. The higher-level models tend to facilitate simulation of longer running workloads (e.g., expected commercial workloads) and can be well-suited for exploring and evaluating key parameters, but they tend not to approach the detail of lower-level models until late in the design process. The lower-level models tend to facilitate more detailed analyses, such as of activity factors and clock-gating opportunities, but their simulations tend to be appreciably more time-intensive and resource-intensive. For example, RTL-based simulations can tend to be impractical for simulating long-running, commercial workloads (e.g., an actual expected workload), such as Standard Performance Evaluation Corporation's (SPEC) standard central processing unit (CPU) workload (“SPEC CPU”), Java business benchmark workload (“SPEC JBB”), Java enterprise edition workload (“SPEC jEnterprise”), etc.
When using lower-level (e.g., RTL) models, simulations often employ “micro-benchmarks” that define specific conditions using appreciably smaller instructions sets to allow the lower-level simulation to run within a reasonable amount of time. For example, tens to hundreds of instructions can correspond to kernels in common algorithms. While such micro-benchmarks are commonly used for power optimization of microprocessor designs, the workload conditions provided by those micro-benchmarks are often appreciably different from dynamic or average behaviors of actual workload conditions.